Lead Design Verification Engineer
Core
Performs functional logic verification of FPGA designs to ensure they meet microarchitecture specifications.
Role type
Lead Design Verification Engineer (FPGA)
Builds
FPGA designs and verification environments
Domain
Semiconductor / Hardware Design
Required skills
OVM/UVM, System Verilog, constrained random verification, gate-level simulation, power analysis, timing analysis, bug debugging, verification planning, test bench development, technical documentation
Preferred skills
Complex IP/SOC verification, complete verification life cycle management, PCIe or UCIe PHY verification, validation test suite development
Technologies
FPGA, System Verilog, OVM, UVM, Gate-level simulation, PCIe, UCIe
Responsibilities
Develop FPGA verification plans, test benches, and verification environments; Execute verification plans and run system simulation models; Debug issues in pre-silicon environments and implement corrective measures; Collaborate with architects, RTL developers, and physical design teams; Document test plans and drive technical reviews; Maintain and improve functional verification infrastructure and methodology.
