ASIC DFT Engineer - Acacia (Hybrid)
Core
Design-for-Testability (DFT) Engineer supporting implementation, validation, and signoff for complex ASIC/SoC designs to ensure high-quality test coverage and manufacturability.
Role type
Senior IC ASIC DFT Engineer
Builds
ASIC/SoC blocks and subsystems with embedded DFT logic for silicon production
Domain
Semiconductor / ASIC Design / Test Engineering
Required skills
Scan insertion, MBIST, ATPG, DFT rule checks, pattern validation, coverage analysis, Tcl/Python/Perl scripting, DFT tool usage (Siemens Tessent, Synopsys DFT Compiler/TestMAX)
Preferred skills
Hierarchical DFT methodology, IJTAG/IEEE 1687/1500, BISR flows, gate-level simulation, silicon bring-up, advanced-node ASIC experience, multi-clock-domain scan implementation
Technologies
Siemens Tessent, Synopsys DFT Compiler, TestMAX, Tcl, Python, Perl, Shell
Responsibilities
Implement and validate scan insertion, scan compression, OCC, MBIST, and boundary scan; Run DFT rule checks and debug scan/clock/reset/test-mode issues; Generate and validate ATPG patterns for stuck-at and transition fault models; Analyze test coverage, pattern count, and compression results; Debug DFT DRC violations, ATPG coverage holes, and pattern simulation issues; Develop automation scripts for DFT flows and reporting; Support block-level and full-chip DFT integration activities.
Seniority
Senior, hands-on IC
