FPGA Development Tools Engineer
Core
Senior Technical Lead driving development, modeling, and validation of FPGA IP and simulation models within the Altera Quartus Prime ecosystem.
Role type
Senior Technical Lead, FPGA IP & Simulation
Builds
FPGA IP blocks, high-fidelity simulation models (behavioral, cycle-accurate), and verification infrastructure
Domain
Semiconductor / FPGA Design
Required skills
RTL design (Verilog/SystemVerilog/VHDL), FPGA IP development, SystemVerilog verification, Assertion-based verification, Quartus Prime toolchain, Debugging complex system-level issues, Testbench architecture, Coverage strategy, Regression systems, Automation (Python/Tcl)
Preferred skills
High-speed interfaces (DDR, PCIe, Ethernet), Timing closure, FPGA architecture and resource mapping, Fitter behavior and constraints, Cross-team technical alignment
Technologies
Altera Quartus Prime, SystemVerilog, VHDL, Python, Tcl
Responsibilities
Define technical direction for IP and simulation models, Lead design reviews and validation strategies, Design and implement FPGA IP and simulation models, Define and enforce robust verification methodologies, Lead debugging of complex issues across simulation and timing analysis, Mentor engineers in debugging and verification practices
Seniority
Senior, hands-on IC with leadership
