Lead Engineer - CAD Physical Verification
Core
Lead Engineer for CAD Physical Verification (PV) supporting chip design and layout teams by debugging PV issues and developing verification rule decks.
Role type
Senior IC physical verification engineer
Builds
Physical verification rule decks (DRC, LVS, Antenna, Dummy fill, PERC, Float, Density, XOR) and automated verification flows
Domain
Semiconductor IC design and manufacturing
Required skills
Calibre SVRF, LVS, extraction, PERC, Python, Perl, Shell, PVS, Pegasus, Calibre RVE, Calibre DRV, Virtuoso
Preferred skills
Custom rule development, impact analysis, tool/feature evaluation, vendor bug tracking
Technologies
Calibre, PVS, Pegasus, Virtuoso
Responsibilities
Debug PV issues for design/layout teams, develop and QA physical verification rule decks, conduct impact analysis meetings, collaborate with CAD/ESD/Design/Layout/Foundry teams, create custom QA testcases, develop PV flows and methodologies, evaluate new tools/features, track bugs with external vendors
Seniority
Senior, hands-on IC
