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Hardware & Physical Engineering
› ASIC Verification Engineering
ASIC Verification Engineering
1,774 open positions
GPU Design Verification Engineer
Apple
Santa Clara, United States of America
8mo
Pre-silicon RTL verification of sub-units in the Apple GPU, ensuring micro-architectural correctness within the broader GPU design.
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Graphics Design Verification Engineer
Apple
Austin, United States of America
8mo
Lead verification for low power embedded graphics cores within high-performance system-on-chip (SoC) designs, ensuring seamless handling of tasks for Apple devices.
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GPU Design Verification Engineer
Apple
Orlando, United States of America
9mo
Verify high-performance, low-power GPU RTL designs using hardware description and verification languages to ensure correctness before silicon fabrication.
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GPU Design Verification Engineer
Apple
Orlando, United States of America
9mo
Pre-silicon RTL verification of embedded graphics cores and post-silicon validation support for high-performance, power-efficient system-on-chip (SoC) GPUs.
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GPU Design Verification Engineer
Apple
Orlando, United States of America
9mo
Lead block and sub-system level pre-silicon RTL verification of embedded graphics cores for Apple's next-generation high-performance, power-efficient system-on-chip (SoC).
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ASIC Design Verification Emulation Engineer
Cisco
San Jose, California, US
$165k
9mo
Define and execute ASIC verification strategy and infrastructure for web-scale and service provider network silicon.
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Staff Verification Engineer
ON Semiconductor
Bangalore, Karnataka, India
9mo
Ensuring quality and reliability of cutting-edge semiconductor designs through comprehensive ASIC verification.
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Calibre Field Application Engineer
Siemens-Eda
Fremont, CA, United States
$167k–$334k
9mo
Provide pre-sale and post-sale technical support for Siemens EDA's Calibre IC physical verification software, driving product adoption and generating leads.
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Staff Verification Engineer
ON Semiconductor
Limerick, Co. Limerick, Ireland
9mo
Creating top-level and block-level verification test plans for power-management integrated circuits to ensure full coverage of hardware and software components.
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Principal Verification engineer
ON Semiconductor
Bangalore, Karnataka, India
9mo
Ensuring functional correctness, robustness, and quality of cutting-edge semiconductor and SoC designs through comprehensive verification planning, testbench development, and advanced simulation techniques.
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Formal Verification Engineer - New College Graduate
NVIDIA
Hungary, Budapest
9mo
Verify the design and implementation of industry-leading GPUs using formal verification algorithms to prove correctness of complex logic problems.
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Design Verification Engineer
Nxp
Pune
9mo
Develop and execute comprehensive verification plans and environments to validate complex digital circuits for semiconductor products.
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DV Intern
Etched
San Jose
9mo
Design Verification intern ensuring custom IPs (systolic arrays, DMA engines, NoCs) are robust, high-performance, and silicon-ready for frontier intelligence chips.
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Staff DFT Design Engineer
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Monolithic Power Systems
Barcelona, CT, ES
9mo
Lead end-to-end design, implementation, verification, validation, and debugging of Digital and Mixed-Signal ICs DFT architectures and solutions.
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Staff DFT Design Engineer
Monolithicpower
Barcelona, Spain
9mo
Leads end-to-end design, implementation, verification, validation, and debugging of DFT architectures for Digital and Mixed-Signal ICs, specifically power management and signal management functions.
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Design Verification Engineer
Apple
Santa Clara, United States of America
9mo
Verify functionality and performance of Apple's System-on-Chip (SOC) designs, including Neural Engine, memory controllers, codecs, security, and high-speed IO.
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Emulation Engineer
Apple
Cupertino, United States of America
9mo
Design and manufacture next-generation, high-performance, power-efficient processor and system-on-chip (SoC) for Apple devices.
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Lead Design Engineer
Cadence
PUNE, IN
9mo
Design and verification of microprocessor cores, multiprocessor sub-systems, and peripherals for Xtensa processors.
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Staff Design Verification Engineer
ON Semiconductor
Bangalore, Karnataka, India
9mo
Define verification plans, lead sub-teams, and develop SystemVerilog/UVM environments for blocks and top-level SoCs.
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CPU Design Verification Engineer - Cork, Ireland
Qualcomm
Cork, Ireland
9mo
Staff CPU Verification Engineer validating CPU and SOC level micro-architectures to ensure launch-ready functionality.
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Analog/Mixed-Signal Design Verification Engineer/Lead
MediaTek
Hefei
9mo
Lead Design Verification efforts for Analog/Mixed-Signal (AMS) IP using UVM-based environments, developing test benches, drivers, checkers, and assertions to achieve functional and code coverage goals.
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Senior ASIC Verification Engineer, Coherent High Speed Interconnect
NVIDIA
Taiwan, Hsinchu
9mo
Verify high-speed coherent interconnect designs, architecture, golden models, and micro-architecture for mobile SoCs and GPUs.
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Senior ASIC Verification Engineer
NVIDIA
India, Hyderabad
9mo
Architect and develop scalable verification flows, CI/CD processes, and automation tools for large IP blocks to streamline CPU and SOC design/verification.
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DFT Engineer (Staff/Senior Staff Level)
MediaTek
Bangalore
9mo
Develop methodologies and implement Design for Test (DFT) for pre/post-silicon flows to ensure test quality for System-on-Chip (SoC), Automotive, and RISC-V products.
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Senior ASIC Verification Engineer
NVIDIA
India, Hyderabad
9mo
Architect and develop tools, user interfaces, and reports to streamline the design/verification of NVIDIA's CPU and SOC designs, focusing on scalable verification flows and continuous integration processes.
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DFT Manager
ON Semiconductor
Bangalore, Karnataka, India
9mo
Lead DFT strategy and architecture for ASIC/SoC products in automotive, industrial, and consumer applications to ensure testability and manufacturability.
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ENGR PRIN, ANALOG; DSGN
ON Semiconductor
Bangalore, Karnataka, India
9mo
Principal Analog Mixed-Signal Verification Engineer responsible for end-to-end verification of Power Management products including DC-DC PMIC, controllers, and drivers for consumer, industrial, and automotive applications.
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Senior Custom SOC IP Verification Engineer
NVIDIA
India, Bengaluru
9mo
Lead ASIC design verification for various processing blocks in a System on Chip (SOC), including planning, execution, coverage, and methodology development.
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Emulation Engineer
Apple
London, United Kingdom
10mo
Building emulation models and verification IP to validate functionality, performance, and power characteristics of Apple's GPU designs.
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ASIC Design Verification Engineer - New College Grad 2026
NVIDIA
US, TX, Austin
$116k–$190k
10mo
Create high-level and broad impact by verifying and improving verification methodologies for system-level IP responsible for measuring performance on multiple projects.
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Senior Verification Engineer - CPU
NVIDIA
US, CA, Santa Clara
$196k–$311k
10mo
Define, plan, and execute performance verification strategy for sophisticated CPU designs, focusing on micro-architectural features and system-level validation.
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Graphics Emulation Engineer
Apple
Austin, United States of America
10mo
Build emulation models and run tests to validate complex GPU microarchitectures for mobile and high-performance devices.
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Senior System Verification Engineer
NVIDIA
US, CA, Santa Clara
$168k
10mo
Senior System Verification Engineer leading emulation environments and verifying high-speed/low-speed protocols for GPUs, SOCs, Switches, and NICs.
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Graphics Verification Software Engineer
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Apple
Austin, TX, US
10mo
Validate complex GPU designs and software through comprehensive hardware/software platform testing to ensure quality standards and seamless execution of demanding graphics workloads.
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Senior Verification Engineer, PCIE
NVIDIA
India, Hyderabad
10mo
Verify ASIC design, architecture, golden models, and micro-architecture of PCI Express controllers at IP/sub-system levels for NVIDIA GPUs and SOCs.
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Design Verification Engineer- Display Interface Protocol Specialist
MediaTek
Bangalore
10mo
Develop and verify Display Port (DP/eDP) IP and subsystems, including DP Tunnelling over USB4, ensuring robust RTL designs through simulation and debugging.
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Design Verification Lead
Apple
Cupertino, United States of America
10mo
Lead design verification efforts for vendor silicon components (power, display, touch, sensors) in mobile products, managing the full project lifecycle from specification to sign-off.
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Staff DFT Solutions Engineer – Chip Methodology & Automation (CMA)
Arm
Bengaluru, India
10mo
Define, develop, and deploy DFT methodologies and flow solutions for Arm-based System-on-Chips (SoCs) to enable efficient deployment across internal teams, customers, and ecosystem partners.
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IC Digital Design Engineer
Aumovio
Bengaluru, KA, in
11mo
IC Digital Design Engineer responsible for IC verification, test architecture, and validation of analog/digital IPs for automotive systems.
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CPU Design Verification Engineer
Apple
Beaverton, United States of America
11mo
Verify functional correctness of CPU design areas by collaborating with architecture and RTL designers to ensure products reach millions of customers.
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CPU Logic Equivalence Check (LEC) Engineer
Apple
Santa Clara, United States of America
11mo
Own logic equivalence check (LEC) and sign-off for Apple's high-performance CPU projects, ensuring functional verification standards are met.
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Design Verification Engineer – CPU Verification
GlobalFoundries
IND - Karnataka - Bengaluru - North
11mo
Functional verification of CPU cores, coherency, and cache subsystems using advanced verification methodologies.
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Senior Verification Engineer - Hardware
NVIDIA
India, Bengaluru
11mo
Create UVM-based verification testbenches and methodologies to verify complex IP and sub-systems for next-generation automotive chips.
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Formal Verification
MediaTek
Bangalore
11mo
Lead formal verification efforts for complex digital designs, ensuring quality and reliability of IP/SubSystem/SoCs.
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Wireless Radio Verification Engineer
Apple
Irvine, United States of America
11mo
Lead verification of Radio digital controllers and Digital+RF subsystems to ensure first-time-right silicon success for Apple's WiFi SoCs.
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Principal Engineer, Design Verification
Analogdevices
United Kingdom, Edinburgh, SC, Freer
12mo
Lead verification efforts for mixed-signal ICs in sensing, signal processing, power management, and audio domains, spanning concept through release.
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Senior RTL Design Engineer
Cisco
Armenia
12mo
Senior RTL Design Engineer driving high-quality Design for Test (DFT) verification and digital design for Cisco Silicon One ASICs.
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Senior Digital Verification Engineer
Monolithicpower
Chengdu - China
12mo
Staff Digital Verification Engineer verifying digital and mixed-signal ICs using industry standard ASIC tools.
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DFT Engineer - Advanced Process Platform(Scan / MBIST / BSD / Silicon Diagnosis)
MediaTek
HsinChu
1y
Define and implement DFT strategies (Scan, MBIST, BSD) for advanced-node SoCs and chiplet/3D-IC designs to ensure ASIC reliability and yield.
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Sr. Digital Verification Engineer (Taipei)
Monolithicpower
Taipei - Taiwan
1y
Verification of digital and mixed-signal ICs for power management, signal management, and mixed-signal functions.
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