Lead Design Engineer
Core
Design and verification of microprocessor cores, multiprocessor sub-systems, and peripherals for Xtensa processors.
Role type
Lead Design Engineer (Logic Design or Design Verification)
Builds
RTL implementations of microprocessor cores and sub-systems; verification environments and test plans for Xtensa processors.
Domain
Semiconductor design IP, system verification hardware, computational software.
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Verilog, SystemVerilog, UVM, SVA, Python, Perl, Tcl, Unix shell, C, assembly language, digital design fundamentals, design verification fundamentals, computer architecture, micro-architecture, EDA simulation, gate-level simulation debugging, ISO 26262 safety concepts.
Preferred skills
Mentoring junior engineers, embedded software understanding.
Technologies
Verilog, SystemVerilog, UVM, SVA, Python, Perl, Tcl, Unix shell, C, assembly language, EDA tools.
Responsibilities
Implement micro-architecture in Verilog RTL, simulate and debug functions, run synthesis and place & route scripts, develop test plans, write functional diagnostics, analyze coverage information, debug failures, work with Design Verification and EDA teams.
Seniority
Senior, hands-on IC
