Senior ASIC Verification Engineer
Core
Architect and develop scalable verification flows, CI/CD processes, and automation tools for large IP blocks to streamline CPU and SOC design/verification.
Role type
Senior IC ASIC Verification Infrastructure Engineer
Builds
Scalable verification flows, automated metrics dashboards, and tooling for chip development
Domain
Semiconductor / ASIC Design / Verification Infrastructure
Deliverable
infrastructure
Required skills
Linux shell scripting, Perl/Python, ASIC EDA tool flows, simulators, waveform debug tools, LSF, Jenkins, Web development (HTML/JavaScript/REST), databases
Preferred skills
RTL design/verification tools (VCS, Verdi), source control systems (Perforce/Git), computer architecture
Responsibilities
Set up scalable verification flows for large IP, improve continuous integration processes, optimize build and simulation flow speed, architect and develop tools for chip development and data visualization, debug complex problems impacting the team
Seniority
Senior, hands-on IC
