Senior Digital Verification Engineer
Core
Staff Digital Verification Engineer verifying digital and mixed-signal ICs using industry standard ASIC tools.
Role type
Staff Digital Verification Engineer
Builds
Power management, signal management, and mixed-signal ICs for portable and non-portable markets.
Domain
Semiconductor / Integrated Power Semiconductors
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, behavioral/RTL coding, ASIC development process, digital design techniques, test plan generation, system-level modeling, test case creation, assertions/checkers, code coverage analysis, gate-level verification, scripting/automation
Preferred skills
Power management industry knowledge, I2C/I3C/SPI/USB/PMBUS/OTP/MTP protocols, Buck/Boost topologies, TCL, Python
Technologies
Digital Simulators, Coverage analysis tools, formal verification tools
Responsibilities
Generate test plans based on design requirements and datasheets; interact with digital and analog designers to develop system-level and behavioral models; create digital verification environments with UVM and SystemVerilog; write digital and mixed-signal testcases and assertions/checkers; analyze and debug test results, code coverage, and functional coverage; document and support detailed test plans and reviews; develop verification IPs and standard tests, environments, and checkers; perform automation and scripting; conduct gate-level verification.
Seniority
Staff, hands-on IC
