Principal Engineer, Design Verification
Core
Lead verification efforts for mixed-signal ICs in sensing, signal processing, power management, and audio domains, spanning concept through release.
Role type
Principal Engineer, Design Verification (SoC/IP level)
Builds
Mixed-signal ICs for portable and non-portable consumer business
Domain
Semiconductor / Analog & Mixed-Signal IC Design
Deliverable
production ML models | product features
Required skills
UVM, System Verilog, Formal verification, constrained random techniques, assertion-based verification, coverage analysis, testbench architecture, debugging, project management, team leadership
Preferred skills
HW emulation, FPGA prototyping, low power methodologies (UPF), behavioral modeling of analog circuits, processor-based design verification, interface protocols (AHB/APB/AXI/I2C/SPMI)
Technologies
UVM, System Verilog, Python, TCL/tsh, Perl, Makefile
Responsibilities
Develop testbench architectures using UVM or Formal approaches; Define verification plans, functional coverage, and tests; Debug Gate Level Simulation and waive timing violations; Mentor junior verification engineers; Lead verification efforts at IP or SoC level including estimation and scheduling; Support post-silicon verification activities
Seniority
Principal, hands-on IC with team leadership