Staff DFT Solutions Engineer – Chip Methodology & Automation (CMA)
Core
Define, develop, and deploy DFT methodologies and flow solutions for Arm-based System-on-Chips (SoCs) to enable efficient deployment across internal teams, customers, and ecosystem partners.
Role type
Staff DFT Solutions Engineer (Chip Methodology & Automation)
Builds
Scalable DFT methodologies, flows, automation, and reference solutions for Arm-based SoCs
Domain
Semiconductor / SoC Design / Digital Test
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DFT implementation and methodology development, Scan/Compression/ATPG/MBIST/LBIST/JTAG/IEEE 1149.x/IEEE 1687, RTL-to-GDS flow integration, EDA tool expertise, Python/Tcl/Shell scripting, Complex SoC debugging
Preferred skills
Advanced-node SoC development, Chiplet/multi-die architectures, CAD/automation infrastructure development, Automotive/safety/production test requirements
Technologies
Python, Tcl, Shell, IEEE 1149.x, IEEE 1687
Responsibilities
Develop and maintain DFT methodologies, flows, automation, and reference solutions; Drive alignment and integration of DFT flows within end-to-end RTL-to-GDS and silicon enablement methodologies; Collaborate with architecture, implementation, CAD, product engineering, customers, and ecosystem partners; Evaluate and enable new capabilities with EDA vendors and technology partners; Lead technical reviews, resolve complex integration challenges, and drive methodology improvements; Mentor engineers and contribute to the DFT and automation roadmap
Seniority
Senior/Lead, hands-on IC with mentorship