Staff Design Verification Engineer
Core
Define verification plans, lead sub-teams, and develop SystemVerilog/UVM environments for blocks and top-level SoCs.
Role type
Staff Design Verification Engineer
Builds
Verification environments and testbenches for digital blocks and System-on-Chips (SoCs)
Domain
Semiconductor / Digital Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, constrained random driven verification, assertion-based verification, regression management, coverage collection, RTL debugging, verification planning, requirements tracking
Preferred skills
Python for automation, C/C++ for embedded software, CPU/MCU verification, SystemRDL, IP-XACT, signal processing verification, 3rd party verification IP deployment
Technologies
SystemVerilog, UVM, Python, C/C++, SystemRDL, IP-XACT
Responsibilities
Define detailed verification plans for blocks and systems, Lead verification activities in smaller sub-teams, Develop SystemVerilog/UVM environments for blocks and top-level SoCs, Debug functional errors in RTL, Support younger engineers on their activities
Seniority
Staff, hands-on IC with mentorship
