Design Verification Engineer- Display Interface Protocol Specialist
Core
Develop and verify Display Port (DP/eDP) IP and subsystems, including DP Tunnelling over USB4, ensuring robust RTL designs through simulation and debugging.
Role type
Senior IC design verification engineer (display interface protocols)
Builds
Display Port (DP/eDP) IP and subsystems
Domain
Semiconductor hardware design and verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
System Verilog, UVM methodology, RTL design verification, simulation, debugging, coverage analysis, testbench development
Preferred skills
Mentorship, cross-functional collaboration, knowledge of DP Tunnelling over USB4
Technologies
System Verilog, UVM, DP/eDP, USB4
Responsibilities
Develop verification plans for DP/eDP and DP Tunnelling over USB4 IP; Create and maintain testbenches using System Verilog and UVM; Perform functional verification of RTL designs including simulation and debugging; Collaborate with designers to understand specifications; Identify and resolve design and verification issues; Generate and analyze verification metrics; Participate in design and verification reviews; Mentor junior verification engineers
Seniority
Senior, hands-on IC
