Analog/Mixed-Signal Design Verification Engineer/Lead
Core
Lead Design Verification efforts for Analog/Mixed-Signal (AMS) IP using UVM-based environments, developing test benches, drivers, checkers, and assertions to achieve functional and code coverage goals.
Role type
Senior IC Analog/Mixed-Signal Design Verification Lead
Builds
Scalable and portable AMS verification environments, test suites, and reference models for IP and chip delivery
Domain
Semiconductor / Analog & Mixed-Signal Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM methodology, AMS DV expertise, RTL simulation, Gate Level simulation, Test bench development, Driver/Checker development, Assertion writing, Coverage closure, Technical leadership, Process improvement
Preferred skills
Global collaboration, Methodology advancement, Resource planning
Technologies
UVM, RTL, Gate Level simulators
Responsibilities
Develop configurable test benches, drivers, checkers, and assertions; Lead DV teams and provide technical guidance; Collaborate with architecture, design, and post-Silicon teams; Drive process improvements for quality and efficiency
Seniority
Senior, hands-on IC with leadership responsibilities