Senior RTL Design Engineer
Core
Senior RTL Design Engineer driving high-quality Design for Test (DFT) verification and digital design for Cisco Silicon One ASICs.
Role type
Senior IC RTL Design Engineer (DFT focus)
Builds
Advanced networking silicon (ASICs) for Cisco Switching, Routing, and Wireless products
Domain
Networking hardware / ASIC design
Deliverable
production ML models | product features
Required skills
ASIC digital design, Verilog/System Verilog, front-end tools (simulation, linting, CDC, synthesis, formal verification), interface protocols (AMBA, JTAG), Python/Tcl/Make scripting
Preferred skills
Power optimization (UPF), DFT/MBIST
Technologies
Verilog, System Verilog, Python, Tcl, Make, AMBA, JTAG
Responsibilities
Drive DFT verification for robust silicon solutions, perform sub-system/SoC integration and verification, review and enhance RTL codes, improve IP/SoC development flows, collaborate with verification teams for complex debugs, interact with physical design teams to optimize QoR
Seniority
Senior, hands-on IC