ASIC Design Verification Engineer - New College Grad 2026
Core
Create high-level and broad impact by verifying and improving verification methodologies for system-level IP responsible for measuring performance on multiple projects.
Role type
entry-level ASIC verification engineer (system-level IP)
Builds
system-level IP for measuring performance
Domain
semiconductor / hardware design
Required skills
System Verilog, UVM, OOPS-based programming, Python, RTL design (Verilog), computer architecture fundamentals, verification tools (VCS, Verdi)
Responsibilities
Design and maintain unit level/sub-system Verification environment; Understand architecture specifications and develop test plans; Create UVM components, sequences, tests and scoreboards; Sign off on verification efforts with high quality code and functional coverage; Launch regressions, resolve issues, and achieve DV milestone targets; Automate manual steps in build, regression, and triage; Collaborate with architects, designers, and software engineers; Pro-actively contribute to improving testbench efficiency.
