DV Intern
Core
Design Verification intern ensuring custom IPs (systolic arrays, DMA engines, NoCs) are robust, high-performance, and silicon-ready for frontier intelligence chips.
Role type
Design Verification Intern
Builds
Custom hardware IPs for inference-focused AI chips
Domain
Hardware engineering / AI Infrastructure
Deliverable
production ML models
Required skills
High-speed digital logic, ASIC/SoC design concepts, SystemVerilog, UVM, Python, verification test benches, physical design flows
Preferred skills
Transformers/ML model architectures, formal verification, scripting languages
Responsibilities
Collaborate with architects and RTL designers to validate correctness and performance across the hardware-software stack
Seniority
Intern
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