Staff Verification Engineer
Core
Ensuring quality and reliability of cutting-edge semiconductor designs through comprehensive ASIC verification.
Role type
Staff ASIC Verification Engineer
Builds
Production ASIC chips
Domain
Semiconductor / Hardware Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, OVM, C++, Perl, Tcl, Python, Verilog PLI, I2C, SPI, UPF, formal verification, constraint random verification, object-oriented programming
Preferred skills
Low-power verification, formal verification techniques
Technologies
SystemVerilog, UVM, OVM, C++, Perl, Tcl, Python, Verilog PLI, I2C, SPI, UPF
Responsibilities
Develop and execute comprehensive verification plans; Create and enhance testbenches using SystemVerilog (OVM/UVM); Implement reusable Verification IP (VIP) components; Apply standard ASIC verification techniques including test planning, testbench creation, code and functional coverage, directed and random stimulus generation, and assertions; Demonstrate solid understanding of ASIC design and verification methodologies; Implement constraint random verification methodology.
Seniority
Staff, hands-on IC
