Formal Verification
Core
Lead formal verification efforts for complex digital designs, ensuring quality and reliability of IP/SubSystem/SoCs.
Role type
Lead Functional Formal Verification Engineer
Builds
Verified digital designs (IP, SubSystems, SoCs)
Domain
Semiconductor / Digital Logic Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
formal verification, property specification languages (SVA, PSL), HDLs (System Verilog, Verilog, VHDL), EDA formal tools, scripting (Python, Tcl, Perl), C/C++/SystemC, technical leadership, mentoring
Preferred skills
CPU/GPU architecture knowledge, industry protocols (AXI, CHI, PCIe), UVM methodology, formal verification performance optimization (abstraction, property decomposition, state-space reduction), Jasper or VC Formal products
Responsibilities
Lead complete formal verification for design blocks and IPs, develop verification strategies and test plans, prove design properties and identify bugs, craft innovative verification solutions, mentor junior team members, collaborate with cross-functional teams
Seniority
Senior, hands-on IC with leadership
