Principal Verification engineer
Core
Ensuring functional correctness, robustness, and quality of cutting-edge semiconductor and SoC designs through comprehensive verification planning, testbench development, and advanced simulation techniques.
Role type
Principal ASIC/SoC Verification Engineer
Builds
Production SoC and IP designs for semiconductor clients
Domain
Semiconductor / Hardware Design Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM/OVM, constrained-random verification, coverage-driven verification, Gate-Level Simulation (GLS), timing verification, power-aware verification (UPF/CPF), formal verification, ARM-based SoC architectures, AMBA protocols (AXI/AHB/APB), Python, Perl, Tcl, C/C++, Verilog PLI, EDA tools (Synopsys, Cadence, Siemens), CI/regression automation
Preferred skills
AI/ML techniques for verification (intelligent stimulus generation, failure triage, coverage optimization), reusable scalable testbench architectures
Technologies
SystemVerilog, UVM, OVM, Python, Perl, Tcl, C/C++, Verilog PLI, Synopsys, Cadence, Siemens, UPF, CPF, AXI, AHB, APB, I2C, SPI, UART
Responsibilities
Develop and execute SoC/IP-level verification plans aligned with design specifications; Architect and enhance SystemVerilog UVM/OVM-based testbenches; Perform Gate-Level Simulation (GLS) including SDF annotation and timing verification; Execute power-aware verification using UPF/CPF; Collaborate with design, architecture, DV, validation, and firmware teams to drive verification to completion.
Seniority
Principal, hands-on IC
