Sr. Digital Verification Engineer (Taipei)
Core
Verification of digital and mixed-signal ICs for power management, signal management, and mixed-signal functions.
Role type
Senior Digital Verification Engineer
Builds
Power management ICs, switching regulators, sensors, motor control, display drivers, audio amplifiers
Domain
Semiconductor / Integrated Power Semiconductors
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, behavioral/RTL coding, ASIC development process, digital design techniques, gate-level verification, coverage analysis, formal verification tools, TCL, Python, C/C++ scripting
Preferred skills
Embedded designs, firmware development, power management industry applications, I2C, I3C, SPI, USB, PMBUS
Technologies
Digital Simulators, Coverage analysis tools, formal verification tools, UVM, System Verilog
Responsibilities
Generate verification plans based on design requirements and product datasheets, Create Digital Verification Environment with UVM and System Verilog, Write Digital and Mixed-Signal testcases and assertions/checkers, Analyze and debug test results, code coverage and functional coverage, Develop Verification IPs and standard tests, environments, checkers, etc., Automation and scripting, Gate-Level verification
Seniority
Senior, hands-on IC