ASIC Design Verification Emulation Engineer
Core
Define and execute ASIC verification strategy and infrastructure for web-scale and service provider network silicon.
Role type
Senior IC ASIC Design Verification Emulation Engineer (Strategy & Architecture)
Builds
Scalable, reusable verification infrastructure and methodologies for complex ASIC programs
Domain
Semiconductor / ASIC Design / Network Infrastructure
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
System Verilog, UVM, emulation methodologies, verification architecture, Python, Perl, C/C++
Preferred skills
Data center/Hyperscaler/AI Networking experience, industry standards authorship, large-scale SoC architecture, advanced emulation/prototyping/formal verification tools, silicon bring-up/debug
Technologies
System Verilog, UVM, emulation tools, Python, Perl, C/C++
Responsibilities
Set vision and strategy for ASIC verification methodology across multiple programs; Serve as technical authority and mentor for verification teams; Lead architecture and implementation of scalable verification infrastructure; Drive cross-functional initiatives to improve verification efficiency and coverage; Influence ASIC architecture to enable robust verification; Provide technical leadership in root cause analysis for complex issues during bring-up and post-silicon validation
Seniority
Senior, hands-on IC with strategic leadership
