Senior/Staff Design Verification Engineer - Coherent Interconnect
Core
Design verification for ARM Neoverse Coherent Mesh Network, a scalable system interconnect for networking, storage, server, HPC, AI, and industrial solutions.
Role type
Senior/Staff Design Verification Engineer
Builds
Next generation of ARM Neoverse coherent interconnect products
Domain
Semiconductor / System-on-Chip (SoC) / Coherent Interconnect
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, constrained-random testbenches, cache coherence, memory systems, bus protocols (AMBA CHI, ACE), verification methodology design
Preferred skills
PCIe, Compute Express Link, Formal Verification, Python, Perl
Technologies
SystemVerilog, UVM, Python, Perl
Responsibilities
Build and maintain detailed verification plans and strategies; Architect and develop efficient SystemVerilog/UVM based test benches; Design new stimulus and coverage, debug functional regression failures, and close coverage; Work alongside architects and designers to debug and develop new features; Develop and drive improvements in verification methodology
Seniority
Senior/Staff, hands-on IC
