UVM Verification specialist for ASIC and/or FPGA development
Core
UVM Verification specialist for complex ASIC and FPGA designs in the telecom sector, ensuring functional correctness and performance through advanced verification methodologies.
Role type
Senior IC Verification Engineer (ASIC/FPGA)
Builds
Verification environments, test benches, and IP blocks for ASIC and FPGA designs
Domain
Telecom, ASIC, FPGA
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM methodology, SystemVerilog, multi-clock domain design, IP block verification, formal verification techniques, coverage modeling, concurrent assertions, protocol knowledge (AXI, AXIS, Avalon-MM, AHB, APB, Ethernet), test bench development from scratch
Preferred skills
C, emulation, Python, Perl, Bash, HLS, constrained randomization, Telecom experience
Technologies
UVM, SystemVerilog, formal verification tools, AXI, AXIS, Avalon-MM, Avalon-ST, AHB, APB, Ethernet
Responsibilities
Develop and execute test plans, test benches, and verification environments; Perform ASIC verification using UVM and SystemVerilog; Work on IP block verification and multi-clock domain designs; Collaborate with design teams to ensure functional correctness and coverage goals; Apply formal verification techniques; Debug and resolve issues efficiently
Seniority
Senior, hands-on IC
