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Design Verification Engineer - APS

Santa Clara, CA, United States💼 Full-time🗓 2026-04-23 → 2026-07-22

Core

Confirm accuracy of analog and mixed signal electronic designs before mask development through independent analysis, experimental testing, and software simulations.

Role type

Senior IC design verification engineer (analog/mixed-signal)

Builds

Verified analog and mixed-signal integrated circuits and components

Domain

Semiconductor hardware / Analog and mixed-signal electronics

Deliverable

production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work

Required skills

UVM, Verilog, SystemVerilog, Python, EDA design tools, UNIX environment, formal verification methods, analog circuit analysis, power systems knowledge

Preferred skills

Developing scalable UVM-based testbenches, driving functional and code coverage closure, code and testbench reviews, methodology improvements

Technologies

UVM, Verilog, SystemVerilog, Python, EDA tools, UNIX

Responsibilities

Analyze equipment to establish operating data, conduct experimental tests, run software simulations, review vendor capability, drive functional and code coverage to closure

Seniority

Senior, hands-on IC

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