CAD Engineer – Design Verification Methodology
Core
Develop, maintain, and enhance sophisticated software systems for regression-testing Apple's silicon designs in software simulation to find and report defects in chip designs.
Role type
Senior IC CAD Engineer (Design Verification Methodology)
Builds
Regression testing systems for Apple silicon designs
Domain
Semiconductor / Chip Design / Design Verification
Required skills
Python programming, Debugging vendor tool problems, System regression (RTL), TCL/Perl scripting, Verilog/SystemVerilog, EDA tool integration (Synopsys VCS/XCelium/Modelsim), Root cause analysis, Scripting (Makefile)
Preferred skills
Artificial intelligence and machine learning, C/C++ programming, VHDL familiarity, Verdi/Indago familiarity, Customer support experience
Technologies
Python, TCL, Perl, Verilog, SystemVerilog, VHDL, Synopsys VCS, XCelium, Modelsim, Verdi, Indago, Makefile
Responsibilities
Develop and maintain regression-testing software systems for silicon designs, Diagnose root causes of complex simulation problems, Collaborate with EDA vendors to incorporate new tool capabilities, Guide engineers in solving design verification issues
Seniority
Senior, hands-on IC
