Lead Design Engineer
Core
Design verification of ASICs for the Palladium product, covering IP, Sub-System, and SOC levels.
Role type
Lead Design Verification Engineer (ASIC)
Builds
ASIC designs for Palladium
Domain
Semiconductor / Hardware Design
Required skills
Verilog, SystemVerilog, Specman e, UVM, OVM, eRM, functional coverage, code coverage, assertions, test plan creation, PCIe verification, LPDDR verification, debugging, scripting/automation
Preferred skills
cross-team communication, documentation
Technologies
Verilog, SystemVerilog, Specman e, UVM, OVM, eRM, PCIe, LPDDR
Responsibilities
Create test plans and functional coverage plans; code functional coverage bins; perform post-silicon validation and bring-up; debug verification issues; develop assertions and closure strategies.
Seniority
Senior, hands-on IC
