ASIC DFT CAD Technical Leader
Core
Lead end-to-end DFT flow architecture and build scalable CAD infrastructure for complex ASIC designs.
Role type
Senior IC ASIC DFT CAD Technical Leader
Builds
Scalable DFT CAD infrastructure, regression frameworks, and AI-driven automation for silicon bring-up.
Domain
Semiconductor / ASIC Design / DFT / EDA
Deliverable
production ML models | infrastructure
Required skills
DFT flow architecture, EDA DFT toolchain (Synopsys TestMAX, VCS, Siemens Tessent), Tcl/Python/Perl scripting, automated flow building, SoC integration, AI/ML for EDA workflows
Preferred skills
Data analytics (Python/pandas), large-scale regression systems, ATE/tester formats (STIL)
Technologies
Synopsys TestMAX, Synopsys VCS, Siemens Tessent, LSF, Python, Tcl, Perl, STIL
Responsibilities
Own and drive end-to-end DFT flow architecture; Build and maintain scalable DFT CAD infrastructure; Develop robust regression frameworks with job orchestration; Lead AI-driven automation initiatives for log analysis and failure triage; Collaborate with RTL, Physical Design, and Validation teams; Define and track key metrics and build dashboards; Standardize flows and enforce best practices; Evaluate and integrate new tools and AI technologies; Mentor and guide engineers.
Seniority
Senior, hands-on IC with mentorship