CAD Engineer – Design Verification Methodology
Core
Develop, maintain, and enhance sophisticated software systems for regression-testing Apple's silicon designs in software simulation to find and report defects in chip designs.
Role type
Senior IC CAD engineer (design verification methodology)
Builds
Regression testing software systems for Apple silicon designs
Domain
Semiconductor / Chip Design / Design Verification
Required skills
Python programming, debugging vendor tool problems, developing regression systems for RTL, diagnosing root causes of complex problems, guiding engineers, interacting with DV teams, implementing new functionality, optimizing existing methods
Preferred skills
TCL or Perl, artificial intelligence and machine learning, Verilog and SystemVerilog, VHDL, Synopsys VCS, XCelium, Modelsim, Verdi, Indago, C and C++, writing build scripts or Makefiles
Technologies
Python, TCL, Perl, Verilog, SystemVerilog, VHDL, Synopsys VCS, XCelium, Modelsim, Verdi, Indago, C, C++
