Senior Engineer
Core
Architecting and implementing verification strategies, testbenches, and test plans for complex SoC and IP blocks using SystemVerilog/Verilog and UVM.
Role type
Senior IC verification engineer (SoC/IP)
Builds
Verified SoC designs and IP blocks
Domain
Semiconductor hardware verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog/Verilog HDL, UVM/OVM, formal verification, C/C++ embedded programming, ARM architecture knowledge, clock domain crossing verification, power aware verification (UPF), DFT/DFD, shell scripting (Tcl/Perl/Python), debugging complex hardware issues
Preferred skills
Experience with GLS, emulation, silicon validation, FPGA development, embedded operating systems, device drivers
Technologies
SystemVerilog, Verilog, UVM, OVM, JasperGold, ARM, Tcl, Perl, Python, UPF, DFT
Responsibilities
Define verification methodologies and test plans, develop reusable verification components, write SystemVerilog/Verilog testbenches, execute formal verification proofs, debug test failures, collaborate with architecture and design teams
Seniority
Senior, hands-on IC