Sr. Physical Design Verification Engineer, Annapurna Labs
Core
Ensure quality and manufacturability of complex semiconductor designs through physical verification processes for custom chips and accelerators.
Role type
Senior IC ASIC Physical Design Verification Engineer
Builds
Custom SoCs, ML inference and training datacenter servers (Inferentia, Trainium)
Domain
Semiconductor / Hardware / Cloud Infrastructure
Deliverable
production ML models
Required skills
Physical verification methodologies, DRC, LVS, PERC, Fill insertion, EDA tools (Calibre, IC Validator), Python/Perl scripting, Backend physical design flows (FC/Innovus), Semiconductor manufacturing processes, Tape-out experience
Preferred skills
Advanced node integration (5nm or below), DFM methodologies, Reliability verification (ESD, EM, IR drop), Layout design, Custom IC development
Technologies
Calibre, IC Validator, PVS, Innovus, FC
Responsibilities
Drive full chip floorplan, integration and physical verification sign-off and closure; Define and optimize physical verification methodologies; Perform DRC, LVS, PERC verification, and Fill insertion; Debug and resolve physical verification issues; Interface with foundries for rule deck updates; Develop and maintain verification runsets; Support technology file development; Mentor junior engineers
Seniority
Senior, hands-on IC