<Data Center>Senior/Lead DFT CAD and Methodology Engineer
Core
Develop and deploy advanced test methodologies and CAD flows for next-generation data center and AI ASICs, focusing on 2.5D/3DIC packaging technologies.
Role type
Senior/Lead DFT CAD and Methodology Engineer
Builds
Test solutions for complex 2.5D/3DIC chiplets and TSV-based 3D stacks
Domain
Semiconductor design, Advanced packaging, AI ASICs
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DFT flow development, ATPG, Memory BIST (MBIST), Python scripting, TCL scripting, Perl scripting, EDA tool integration, 3DIC/2.5D testing strategies, technical mentorship
Technologies
Python, TCL, Perl, EDA tools
Responsibilities
Develop and deploy robust CAD flows for scan insertion, ATPG, pattern simulation, and Memory BIST; Create scripts to automate DFT flows and improve simulation runtimes; Collaborate with EDA vendors to enhance tools for advanced packaging; Support DFT integration teams with CAD flow issues and debug complex problems; Develop and implement testing strategies for chiplets and TSV-based 3D stacks
Seniority
Senior/Lead, hands-on IC
