Principal Engineer, Design Verification Engineering
Core
Lead design verification for mixed-signal power converter controllers from architecture through silicon bring-up, ensuring tape-out readiness and quality metrics.
Role type
Principal Engineer, Design Verification Engineering (Mixed-Signal/Power)
Builds
Industry-leading DC-DC converter controllers for datacenter and energy applications
Domain
Semiconductor / Power Management / Mixed-Signal IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog/UVM, constrained-random verification, self-checking testbenches, verification sign-off (coverage, assertions/SVA, LINT, CDC/RDC), formal/semi-formal techniques, behavioral modeling (Verilog-AMS), mixed-signal co-simulation, regression automation, mentoring
Preferred skills
Xcelium/VCS/Questa simulators, Python/Tcl scripting, AI tools for verification, integrated power management domain knowledge (buck/boost converters, control loops)
Technologies
SystemVerilog, UVM, Verilog-AMS, Python, Tcl, Xcelium, VCS, Questa, LINT, CDC/RDC tools
Responsibilities
Provide technical leadership for verification strategy and execution; own end-to-end verification plans and sign-off criteria; develop and review SystemVerilog/UVM testbenches; translate system requirements into verifiable specifications; drive coverage methodology and closure; build scalable regression infrastructure; lead AMS verification with behavioral models; partner with design teams for silicon bring-up and root-cause analysis; mentor verification engineers and drive methodology improvements
Seniority
Principal, hands-on IC design verification with technical leadership
