CPU Debug and Power Management Verification Engineer
Core
Verify auxiliary features (Power Management, Clock Control, Debug Infrastructure) of a high-performance ARM-based CPU across the product lifecycle.
Role type
Senior IC design verification engineer (CPU auxiliary features)
Builds
Robust, low-power, high-performance CPU designs for Apple hardware
Domain
Semiconductor / CPU Design Verification
Required skills
SystemVerilog, SVA, C++, Assembly, Perl/Python, UVM, random constraint verification, functional coverage analysis, silicon bring-up debugging, waveform/trace tool usage
Preferred skills
Processor architecture knowledge, power management architecture, AXI protocols, formal verification, hardware trace features, object-oriented programming
Technologies
SystemVerilog, SVA, C++, Perl, Python, UVM, FPGA, Emulation, Silicon, Waveform tools, Trace tools
Responsibilities
Develop and execute test plans for CPU Power Management, clock control, and debug logic; Write and debug tests in simulation, emulation, and FPGA environments; Build verification infrastructure including checkers and coverage monitors; Identify, root-cause, and document design issues; Collaborate with RTL teams to drive fixes; Support SoC-level debug for clock and power integration issues; Contribute to post-silicon debug using waveform and trace tools
Seniority
Senior, hands-on IC
