Staff Verification Engineer - System IP
Core
Verification of complex System IP (CoreLink/CoreSight) for compute solutions in mobile, servers, and autonomous vehicles.
Role type
Staff Verification Engineer (System IP)
Builds
System IPs for interrupt control, inter-process communication, trace, and debug solutions
Domain
Semiconductor / Hardware Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL verification of complex ASIC products, SystemVerilog, UVM, coverage-driven constrained random test environments, functional coverage closure, Verilog RTL debugging, computer architecture fundamentals
Preferred skills
Python, Perl, formal verification techniques, object-oriented programming, data structures, algorithms
Technologies
SystemVerilog, UVM, Verilog
Responsibilities
Develop comprehensive verification strategies, create and review design verification documentation, design and implement verification IP and testbenches, improve existing testbenches for performance and efficiency, test and debug Verilog RTL, define and implement functional coverage, plan and track tasks to meet targets, drive execution for quality and on-time delivery, coach and mentor junior engineers
Seniority
Staff, hands-on IC with mentorship