Wireless Radio Verification Engineer
Core
Verify Radio digital controllers and RF subsystems to ensure first-time-right silicon success for multi-gigabit wireless technology.
Role type
Senior IC verification engineer (digital/mixed-signal)
Builds
Verification environments, testbenches, and scenarios for complex radio control and transceiver paths
Domain
Consumer electronics, wireless connectivity, semiconductor verification
Required skills
SystemVerilog, UVM, RTL simulation, Python scripting, digital design fundamentals (Verilog/VHDL), constrained random testing, functional coverage, mixed-signal modeling concepts
Preferred skills
RF/analog system design exposure (PLLs, DAC/ADCs, LNAs, Mixers), assertion-based verification, Perl/Bash scripting
Technologies
SystemVerilog, UVM, Python, Verilog, VHDL, DMS models
Responsibilities
Develop UVM testbench environments and bus functional models for radio control and datapath subsystems. Implement constrained random scenarios to exercise radio protocols and state machine interactions. Collaborate on digital + mixed-signal verification using SystemVerilog analog behavioral models. Drive closure by tracking regressions, debugging issues, and addressing coverage gaps. Partner with cross-functional teams to define verification strategy. Develop Python automation for verification flows and regression infrastructure.
Seniority
Senior, hands-on IC
