ASIC Emulation Engineer / Technical Leader
Core
Define, design, and develop emulation environments for complex, large-scale networking ASICs to speed up development and identify pre-silicon issues.
Role type
Senior IC ASIC Emulation Engineer / Technical Leader
Builds
Emulation infrastructure and environments for multi-terabit systems
Domain
Networking hardware, ASIC design and verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
System Verilog, Verilog, C/C++, TCL, Python, RTL development, emulation platform expertise (Veloce/Palladium/Zebu), system debug (gdb, waveform debuggers), ASIC design and verification flow knowledge
Preferred skills
Scripting (Perl), post-silicon functional validation, protocol knowledge (PCIe, I2C, Ethernet), validated leadership
Technologies
Veloce, Palladium, Zebu, C/C++, TCL, Python, System Verilog, Verilog, gdb
Responsibilities
Develop emulation flows and test plans to generate complex traffic and performance scenarios; collaborate with design, DV, power, and post-silicon diagnostic teams; troubleshoot issues with emulation vendors; assist in debugging during pre-silicon emulation process.
Seniority
Senior, hands-on IC with leadership responsibilities
