ASIC Emulation Engineer / Technical Leader
Core
Define, design, and develop emulation environments for complex, large-scale networking ASICs to speed up development and find pre-silicon issues.
Role type
Senior IC ASIC Emulation Engineer / Technical Leader
Builds
Emulation infrastructure and environments for multi-terabit systems
Domain
Networking ASICs and Hardware Verification
Required skills
System Verilog, Verilog, C/C++, TCL, Python, RTL development, emulation platform expertise (Veloce/Palladium/Zebu), system debug (gdb, waveform debuggers), ASIC design and verification flow
Preferred skills
Scripting (Python, Perl), post-silicon functional validation, protocol knowledge (PCIe, I2C, Ethernet), validated leadership
Technologies
Veloce, Palladium, Zebu, C/C++, TCL, Python, System Verilog, Verilog, gdb
Responsibilities
Develop state-of-the-art emulation environments; develop and test emulation flows; collaborate with design and hardware teams; assist with test plan design and debugging; develop tests for complex traffic and performance scenarios.
Seniority
Senior, hands-on IC with leadership responsibilities
