CPU Debug and Power Management Verification Engineer
Core
Verify auxiliary features (Power Management, Clock Control, Debug Infrastructure) of a high-performance ARM-based CPU across the product lifecycle.
Role type
Senior IC design verification engineer (CPU)
Builds
Robust, low-power, high-performance CPU designs
Domain
Semiconductor / CPU Design Verification
Required skills
SystemVerilog, SVA, C++, Assembly, Perl/Python, UVM, random constraint verification, functional coverage analysis, test plan development, root-cause analysis, waveform/trace tool usage
Preferred skills
Processor architecture knowledge, power management architecture, system fabric protocols (AXI), formal verification, silicon bring-up experience, hardware trace features, object-oriented programming
Technologies
SystemVerilog, SVA, C++, Perl, Python, UVM, AXI, FPGA, Emulation, Silicon
Responsibilities
Collaborate with architecture and RTL designers on verifying CPU Power Management, clock control, and debug logic; Develop and execute test plans and schedules; Write and debug tests in Assembly, SystemVerilog, SVA, C++, and scripting languages; Build and maintain verification infrastructure including checkers, transactors, and coverage monitors; Analyze functional coverage to ensure test plan completeness; Identify, root-cause, and document design issues and collaborate with RTL teams to drive fixes; Support SoC-level debug for clock and power integration issues; Work with silicon bring-up teams to develop tests and debug issues across emulation, FPGA, and silicon.
Seniority
Senior, hands-on IC
