ASIC Physical Design
1,643 open positions
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Timing Design Engineer AppleBeaverton, United States of America 8mo Ensuring timing sign-off and developing STA flows for SoC design across synthesis to sign-off.
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Sr Principal ASIC / RTL Design Engineer ON SemiconductorBangalore, Karnataka, India 8mo Senior Principal Digital Design Engineer developing power management products (DC-DC PMIC, controllers, SiC drivers) for consumer, industrial, and automotive applications.
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Senior Physical Design Engineer - Signoff Methodology CiscoArmenia 8mo Develop and refine backend methodologies and flows from RTL to GDS, focusing on signoff disciplines for high-quality VLSI designs.
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Digital Design Engineer (New Grad) MonolithicpowerTaipei - Taiwan 8mo Design, development, and verification of digital and mixed-signal integrated circuits (ICs) for power management and portable/non-portable markets.
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Datacenter GPU Power Architect NVIDIAUS, CA, Santa Clara $116k–$116k8mo Develop state-of-the-art GPUs and power estimation models to deliver exceptional performance-per-watt solutions for AI, HPC, Automotive, GeForce, and Mobile products.
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Senior Digital Design Engineer MediaTekCairo 8mo Architecting, designing, and integrating PHY IP blocks for high-speed interfaces within System-on-Chip (SoC) solutions.
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Staff Design Engineer - Video ArmMultiple locations 9mo Design and test hardware modules for Image Signal Processors (ISPs), Display Processors, and Video codecs within Arm Compute Subsystems.
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Digital Design Engineer Texas InstrumentsBengaluru, Karnataka, India 9mo Design and implementation of digital logic at the RTL level for ASICs or SoCs from specification to tape-out.
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Principal Engineer, STA & Synthesis Renesas-ElectronicsHyderabad, in 9mo Own synthesis and timing closure sign-off for low-power, chiplet-based MCU designs on cost-optimized mature process nodes.
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IC Design Engineer SilabsSingapore 9mo Designing digital blocks and integrating them into highly integrated mixed-signal SoCs for low-power MCU and Wireless products.
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Staff Logic Design Engineer FlirUS - Milpitas, CA $142k–$142k10mo Architect and implement high-performance digital logic for protocol capture, analysis, and emulation in FPGA-based systems.
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Lead RTL Design Engineer CerebrasHeadquarters/Sunnyvale Office $175k–$175k10mo Lead RTL design engineer developing the Cerebras Wafer Scale Engine (WSE) architecture for high-performance AI training and inference.
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