Timing Design Engineer
Core
Ensuring timing sign-off and developing STA flows for SoC design across synthesis to sign-off.
Role type
Senior IC ASIC STA Engineer
Builds
SoC designs with verified timing constraints
Domain
Semiconductor / ASIC Design
Required skills
ASIC timing closure flow, STA tools (Primetime), timing corners/modes, process variations, signal integrity, SDC constraints generation, scripting (Tcl, Perl), synthesis methodology, DFT methodology, backend tools
Preferred skills
None explicitly stated beyond minimum qualifications
Technologies
Primetime, Tcl, Perl
Responsibilities
Develop STA and sign-off flow, own IP and block-level timing constraints, interact with RTL designers to understand clock structure, collaborate with Physical design team for timing closure, verify timing constraints, innovate timing constraints to address pessimism or fallouts
Seniority
Senior, hands-on IC
