SoC Physical Design Engineer (M, F, D)
Core
Own block-level physical design implementation from netlist to GDS delivery for complex SoCs using new process technology.
Role type
Senior IC SoC Physical Design Engineer
Builds
SoC chips for Apple hardware products
Domain
Semiconductor / SoC Physical Design
Required skills
Place & Route (PnR) tool expertise (Synopsys/Cadence), static timing closure, power and noise analysis (EM/IR-Drop/Xtalk), layout verification (DRC/LVS), low power clock network guidelines, scripting (Perl/TCL/Make), hierarchical design approach, timing and physical convergence, static-timing analysis, clock/power distribution, RC extraction, mixed-signal IP integration, I/O integration
Preferred skills
Large SoC design experience (>20M gates), high-frequency design (>1GHz), Verilog knowledge
Technologies
Synopsys, Cadence, Perl, TCL, Make
Responsibilities
Own implementation of design partitions (Netlist to GDS), perform static timing closure, conduct power and noise analysis, execute layout verification, develop low power clock network guidelines, resolve physical design flow issues, create design guidelines and specs
Seniority
Senior, hands-on IC
