SoC Physical Design Engineer, PnR
Core
Lead physical design implementation for high-performance, low-power SoCs from RTL to GDS, optimizing timing, area, and power.
Role type
Senior IC SoC Physical Design Engineer (PnR)
Builds
High-performance System-on-Chip (SoC) dies
Domain
Semiconductor / VLSI Physical Design
Required skills
RTL-to-GDS flow, PnR, bump/RDL, STA, physical verification, EMIR, sign-off, timing closure, area optimization, power optimization
Preferred skills
Floorplanning, clock & power distribution, PD construction & analysis flows, large SOC design (>20M gates), deep submicron tapeout experience, industry standard tools expertise
Technologies
Industry standard physical design tools
Responsibilities
Drive methodologies and best-known methods to streamline physical design work; develop guidelines and checklists; solve challenging timing closure issues; collaborate with cross-functional teams on physical architecture
Seniority
Senior, hands-on IC
