ASIC Physical Design
1,648 open positions
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CPU Implementation Engineer AppleAustin, United States of America 1y Design and implement CPU blocks, focusing on memory subsystems, RTL-to-GDS flow, and physical design validation.
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Senior FPGA Design/Verification Engineer LumentumCanada - Ottawa (Bill Leathem) 1y Design and verify control and datapath logic for next-generation optical switches and amplifiers in high-speed data transmission systems.
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SOC DFT Engineer MediaTekHefei 1y Define SOC chip-level and sub-system level DFT architecture, manage scan insertion and timing constraints, and support post-silicon diagnosis and manufacturing process (MP) issues.
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Principal Engineer, Performance Modelling Renesas-ElectronicsRemote 1y Develop and maintain performance models for System-on-Chip (SoC) designs using Platform Architect or Emulation Platform to optimize performance and ensure successful product delivery.
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RTL Design Engineer EtchedSan Jose 1y Develop and implement design verification strategies for AI chips (ASICs) focused on inference workloads, ensuring correct and efficient operation of high-speed digital logic blocks.
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Sr Principal Application Engineer CadenceNOIDA 1y Technical leadership for FPGA-based hardware emulation and prototyping solutions, bridging customers, sales, and R&D to secure design wins.
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STA methodology engineer NxpBangalore 1y Benchmark logic libraries across advanced technology nodes (40nm to 5nm) using synthesis and PNR flows to ensure robust STA methodologies for real-world chips and blocks.
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ASIC/SOC CAD Engineer
MatXMountain View (HQ) or Remote
$160k–$160k2y
Develop, maintain, and improve Physical Design CAD flow and infrastructure to produce performant silicon for high-performance GenAI products.
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ASIC/SOC Silicon Physical Design Engineer
MatXMountain View (HQ) or Remote
$160k–$160k2y
Developing performant and functionally correct silicon for high-performance and sustainable GenAI across compute, memory management, and high-speed connectivity.
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Sr. Digital Implementation Engineer AlifsemiIrvine, CA 3y Creating turn-key solutions for Cellular IoT devices by owning netlist delivery to Physical Design and ensuring RTL database integrity.
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