ASIC Design Engineer – Fabric/Interconnect
Core
Design and integration of coherent and non-coherent interconnect fabrics (NoC, crossbars) and memory hierarchies into SoC subsystems.
Role type
Senior ASIC Design Engineer (Fabric/Interconnect)
Builds
High-performance, low-power SoC components and subsystems
Domain
Semiconductor / ASIC Design
Required skills
RTL development, NoC topology design, crossbar architecture, arbitration logic, IP integration, timing closure, power optimization, verification collaboration
Preferred skills
Cache coherency protocols (MESI, MOESI), directory-based coherence, large-scale production design experience, front-end tooling (lint, CDC, synthesis)
Technologies
RTL, NoC, crossbars, synthesis tools, CDC tools
Responsibilities
Design and integrate interconnect fabrics into SoC subsystems; Own RTL development, templating, and scripting; Collaborate with synthesis, STA, power, and verification teams; Integrate shared IP blocks for memories and hard macros; Ensure designs meet timing and quality standards; Coordinate with multi-disciplinary groups to deliver on schedule
Seniority
Senior, hands-on IC
