Cellular SoC Frontend STA Engineer (m/f/d)
Core
Focal point for constraint development and design/timing analysis for Cellular SoC integration, serving as the link between digital, mixed-signal, and physical design teams.
Role type
Senior IC Frontend Static Timing Analysis (STA) Engineer
Builds
Cellular System-on-Chip (SoC) designs for Apple hardware products
Domain
Semiconductor / SoC Design / Digital & Mixed-Signal Integration
Required skills
Static Timing Analysis (STA), constraint development, multi-mode multi-corner analysis, hierarchical design, timing budgeting, asynchronous interfaces, DFT, timing/physical convergence, scripting (TCL, Perl, Shell, Bash, Python), Linux, Verilog, RTL/Netlist analysis
Preferred skills
RTL design, SoC practices, mixed-signal IP integration, power/performance/area optimization, synthesis flows, logic equivalence checking, ECO implementation
Technologies
PrimeTime, Tempus, PerForce
Responsibilities
Develop constraints for synthesis, PnR, and sign-off STA; verify results post-synthesis for all STA modes; collaborate with digital designers to optimize power, performance, and area; improve development flows with CAD and PD teams.
Seniority
Senior, hands-on IC
