CPU CDC/STA Engineer
Core
Developing, maintaining, and improving CDC, RDC, and STA constraints and methodology for CPU designs across multiple design sites.
Role type
Senior IC CPU CDC/STA Engineer
Builds
CPU designs with verified timing and clock/reset domain integrity
Domain
Semiconductor hardware design (CPU)
Required skills
Static Timing Analysis (STA), Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), System Verilog, TCL scripting, Perl scripting, RTL design, EDA tool debugging
Preferred skills
SystemVerilog Assertions (SVA), Design Verification (DV) simulations, Spyglass, VC-Static, PrimeTime, Meridian, Verilog
Responsibilities
Develop and maintain CDC/RDC sign-offs; Recommend System Verilog assertions for constraints; Develop and enhance STA checks; Debug vendor tool problems; Collaborate with EDA vendors on improvements; Work with RTL, Verification, CAD, and Physical Design teams
