ASIC DFT STA Technical Lead
Core
Lead Static Timing Analysis (STA) and Design for Test (DFT) for next-generation networking ASICs, ensuring timing closure and quality across implementation and post-silicon phases.
Role type
Senior IC ASIC DFT STA Technical Lead
Builds
Silicon One networking chips (Switching, Routing, Wireless)
Domain
Semiconductor / Networking Hardware
Deliverable
production ML models | product features
Required skills
Static Timing Analysis (STA), timing constraint development (SDC), DFT methodologies, RTL design, CDC/RDC verification, scripting (Perl/TCL/Python/Makefile), physical design signoff
Preferred skills
PCIe timing constraints, TSMC memory timing, DFT modes (scan shift/capture, BIST), Synopsys TCM/Primetime, Synopsys Fusion/design Compiler, Tessent DFT insertion
Technologies
Synopsys TCM, Synopsys Primetime, Synopsys Fusion, Synopsys design Compiler, Tessent, Perl, TCL, Python, Makefile
Responsibilities
Develop timing constraints at block, sub-chip, and full-chip levels in test modes; perform quality checks on constraints (duplicates, promotion/demotion); check timing for unconstrained endpoints and no-clock scenarios; develop SDC validation and CDC delay check methodologies; create guidelines and checklists to streamline STA work and resolve flow issues.
Seniority
Senior, hands-on IC
