DMTS NOC Cache Coherency Architect
Core
Architecting and leading design efforts for Network-on-Chip (NOC), Coherency Manager, and Cache Controller components in high-performance multicore/multicluster processors.
Role type
Senior IC Cache Coherency Architect
Builds
High-performance CPU cores and complex SoCs
Domain
Semiconductor design, CPU architecture, interconnect protocols
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Multicore/multicluster coherency design, Cache Controller architecture, SystemVerilog, Verilog, C/C++, Assembly, AXI/ACE/OCP/CHI protocols, Python/Perl/TCL/Shell scripting, CPU architecture knowledge (RISC-V/ARM/MIPS)
Preferred skills
RISC-V architecture expertise, functional safety standards (ISO 26262), FPGA prototyping, emulation platforms
Technologies
SystemVerilog, Verilog, C, C++, Python, Perl, TCL, Shell, AXI, ACE, OCP, CHI, RISC-V, ARM, MIPS
Responsibilities
Lead architectural specification and design for Coherency Manager and Cache Controller IP; Collaborate with design teams to interpret microarchitectural specifications; Automate and optimize verification flows using scripting languages; Mentor design engineers
Seniority
Senior, hands-on IC
