DMTS NOC Cache Coherency Architect
Core
Architecting and leading the design of Network-on-Chip (NOC), Coherency Manager, and Cache Controller components for high-performance multicore/multicluster processors.
Role type
Senior IC Cache Coherency Architect
Builds
High-performance CPU cores and complex SoCs
Domain
Semiconductor / CPU Architecture / Interconnect
Required skills
Multicore/Multicluster Coherency, Cache Controllers, SystemVerilog, Verilog, C/C++, Assembly, AXI/ACE/OCP/CHI protocols, Python/Perl/TCL/Shell scripting, CPU architectures (RISC-V/ARM/MIPS)
Preferred skills
RISC-V architecture, Functional safety (ISO 26262), FPGA prototyping, Emulation platforms
Technologies
SystemVerilog, Verilog, C, C++, Python, Perl, TCL, Shell, AXI, ACE, OCP, CHI, RISC-V, ARM, MIPS
Responsibilities
Lead architectural specification and design for Coherency Manager and Cache Controller IP; Collaborate with CPU core architects and design teams; Automate and optimize verification flows using scripting languages; Mentor design engineers
Seniority
Senior, hands-on IC
