Principal ASIC Physical Design Engineer
Core
Lead the implementation of complex SoCs for next-generation satellite and space systems, owning the full physical design flow from RTL handoff to GDSII.
Role type
Principal ASIC Physical Design Engineer
Builds
High-power, radiation-hardened SoCs for LEO to deep space satellite platforms
Domain
Aerospace / Semiconductor Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL-to-GDSII flow expertise, timing closure, IR drop analysis, ECO implementation, multi-clock/multi-voltage SoC constraints, advanced FinFET process nodes, vendor/partner management, DFT integration, power domain implementation (UPF/CPF)
Preferred skills
Radiation-hardened ASICs, chip-package co-design, advanced packaging (2.5D/3D), TSMC tapeout experience, Gate-All-Around technologies
Technologies
Synopsys, Cadence, Siemens, TSMC
Responsibilities
Own complete RTL-to-GDSII flow including synthesis, floorplanning, place & route, CTS, STA, and physical verification; Develop and maintain physical design methodologies and automation; Collaborate with front-end and verification teams for clean handoffs and timing closure; Drive timing closure across multiple voltage and process corners; Partner with package, SI/PI, and test teams for chip-to-board integration; Manage and guide external physical design partners and service vendors; Work with EDA vendors to debug and optimize tool flows; Support chip bring-up, debug, and production support
Seniority
Principal, hands-on IC with mentorship
