Senior ASIC Hardware Design Engineer
Core
Design and implement next-generation NVLink protocol and GPU subsystem logic for high-speed chip-to-chip communication and high-performance, low-power GPU and interconnect subsystems.
Role type
Senior ASIC Hardware Design Engineer (NVLink/GPU)
Builds
Next-generation NVLink protocol, GPU subsystem logic, and high-performance interconnect subsystems
Domain
Semiconductor / VLSI / GPU Architecture
Deliverable
production ML models
Required skills
Verilog, SystemVerilog, RTL development, micro-architecture design, logic optimization, physical implementation (VLSI), scripting (Perl/Python), timing closure, power/clock distribution, back-end verification
Preferred skills
Low-power build methodologies, high-speed build methodologies, complex design implementation track record
Technologies
NVLink, RTL, VLSI, Perl, Python
Responsibilities
Engage in design and development of NVLink protocol and GPU subsystem logic; Contribute to micro-architecture development and document specifications; Implement in RTL and debug designs; Optimize designs for performance and power goals; Deliver synthesis/timing clean designs; Support hardware engineering activities including floor planning, power/clock distribution, and back-end verification
Seniority
Senior, hands-on IC
