R&D Engineer IC Design 4
Core
Front-end design and verification of design blocks for ASIC cores, translating system requirements into logic and ensuring timing closure.
Role type
Senior IC ASIC Design Engineer
Builds
ASIC design blocks and cores
Domain
Semiconductor / ASIC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL design, Verilog simulation, architecture definition, logic synthesis, timing analysis, formal verification, DFT methodology, TCL/Perl scripting, version control
Preferred skills
Experience with high-frequency designs and advanced technology nodes
Technologies
Synopsys Design Compiler, Cadence RTL Compiler, Synopsys Primetime, Synopsys Formality, Cadence Conformal, Spyglass Lint
Responsibilities
Define architecture and design logic blocks from system requirements; perform simulation, formal verification, and timing analysis; debug designs using Verilog; develop constraints and analyze timing from physical implementation.
Seniority
Senior, hands-on IC
